The trend in the semiconductor industry is the development of submicron level integrated circuits (IC or chip). The use of the IC involves interconnection between the IC and the surface or device where it is positioned. Interconnection include silicon chip connection between chip and lead frame or board; printed wiring connecting individual components; and interconnection between printed wiring boards. Of these interconnections, chip to board interconnection failure is the cause of the majority of failures of electronic systems or devices. Of interconnection failures, solder related interconnection failures are the largest contributors to electronic package failure.
Interconnection provide mechanical, thermal, and electrical functions in the electronic package. Various technologies have been developed to solve this problem of interconnection between chips and the chip and the circuit board. The pin in hole or pin through hole was the traditional method, until the late 1980's when the surface mount technology was introduced. The introduction of the surface mount technology revolutionized the electronic packaging industry. Surface mount technology includes flip chip, chip-on-chip, tape automated bonding, ball grid array and multi-chip module. Each of these techniques differ in its circuitry design and interconnections. U.S. Pat. No. 5,801,447 to Hirano et al., a flip chip mounting type device having a gate region for injection of a sealing member filled between a mounted board and the chip.
Solders have been successfully used for interconnections. Solder fluxes and solder powders have been combined into paste and is easily applied to component foot print areas. Various interconnection methodologies such as vapor phase, convection, laser, infrared, and hot-bar reflow are in use today. With the surface mount technology solder interconnection will continue to be the most reliable, with case of interconnection, and cost effective method. However, failure in solder interconnection are due to the following: mechanical failure due to weakness in material strength, surface tension effect, high temperature creep and plastic deformation, excessive void, intermetallic compound formed at interfaces, the development of damaging microstructures, fatigue failure due to corrosion, and mismatch in coefficient of thermal expansion (CTE).
The joint material causes serious failure due to stress as a result of CTE mismatch. The thermal environment experienced by electronic circuits varies greatly encompassing a range of -50 degrees to +200 degrees F., or more. The CTE of plastic/ceramic is approximately 20 times the CTE of the silicon chip. One solution is to use strain buffers between the low CTE silicon and the high CTE metal. At present solders will strain buffers such as copper and molybdenum are in use. The strain at the solder joints due to temperature change, and fatigue failure of solder interconnections remain high. U.S. Pat. No. 5,170,329 to Purdes discloses a chip mount to reduce stresses caused by thermal expansion mismatch between chip and printed circuit board including a strip member secured to the chip and a guide layer secured to the circuit board.
Typically a packaging scheme may require high heat removal, combined with low stress at the interconnection between chip and board. Thus the interconnection materials should have high thermal conductivity to dissipate heat produced by the chips, with close match between the CTE of the chip and the substrate to minimize thermal stress. However, most of the work in electronic packaging is concerned with packaging schemes rather than materials. The chip or die is attached to the substrate or printed circuit board (PCB) on which interconnection lines have been written (usually by screen printing) on each layer of multilayer substrate or board. In the first level packaging the chip (or chips) may be attached to substrate via soldered joints and the substrate attached to the PCB via soldered joints. In the direct chip attach module (DCAM), the chip is attached directly to the PCB. In the multichip module laminate (MCML), the chip is attached via cardlet, with one or many card attached to a large card. The MCML allows for denser packaging. In surface mount technology (SMT) the surface patterns of conductors are connected electrically without employing holes. Solder is used to make electrical connection between the surface mount package (leaded or leadless) and a circuit board. An examination of conventional pin-through-hole (PTH) technology and high density packaging based on surface mount technology (SMT) provides clues as to the failure mechanism.
One approach to meet the needs of advanced material in electronic packaging is to create new composite materials. Composite materials consists of two or more constituents, with each one maintaining distinct properties and regions. Accordingly alloys are not composites.
One of the well-established composite is the glass fiber reinforced polymer (GFRP) for printed circuit boards. However the recent advanced composites provide unique advantages by being able to tailor their CTE, with high thermal conductivity, low density, and with high strength, and stiffness. At present, the leading composites of interest for applications such as heat sinks and packages are carbon fiber reinforces epoxy (C/Ep), carbon fiber reinforced aluminum (C/Al), carbon fiber reinforced copper (C/Cu), boron fiber reinforced aluminum(B/Al) and silicon carbide particle reinforced aluminum(SiC)-p/Al). Fiber reinforced composites are strongly anistropic; their properties depend strongly on fiber direction. In contrast, monolithic and particle reinforced metals tend to be isotropic; their properties are the same in every direction. Mechanical and physical properties of fiber reinforced materials can be tailored over wide ranges by selection of fiber, matrix, fiber volume fraction, and fiber orientations. It is known that the isotropic inplane CTE of copper reinforced with a variety of pitch-based carbon fibers varies with fiber volume fraction. By varying fiber volume fraction, Vf, it is possible to match the CTE of virtually all materials of interest, including silicon, gallium arsenide, alumina, beryllia and aluminum nitride. The inplane thermal conductivity of C/Cu composites vary with Vf. Note they are much higher than those of conventional packaging materials with low CTE's. Through-thickness conductivities are also high. The CTE and thermal conductivity of carbon fiber reinforced aluminum vary with fiber volume fraction. Another important composite material is reinforcing aluminum alloys with silicon carbide particles. The purity of SiC plays an important role here, and high purity particles have higher thermal conductivities.
The most common composites consists of a matrix reinforced with continuous or discontinuous fiber whiskers, or particles. The four key classes of composites are polymer-matrix composites (PMC's), metal matrix composites (MMC's), ceramic-matrix composites (CMC's) and carbon/carbon (C/C) composites. In addition, there are composites in which the phases have amorphous geometries. For example, some circuit breaker contacts are made by infiltrating silver into a porous preform made by sintering tungsten particles, in essence a metal/metal composite.
The problem associated with brazes and solders can be alleviated by the use of composites brazes or solders which contain a filter of low CTE. Graphite is a suitable filler for alloys typically used for brazing and soldering, such as silver-based braze alloys and tin-based solder alloys. Carbon fibers have been successfully used as a filler for both brazes and solders. Either short or continuous carbon fibers can be used. Short fibers are needed if the solder or braze is to be applied in the form of a paste. Continuous fibers are more effective than short fibers in decreasing the CTE, but they cannot be in a paste form and are thus limited to applications in solder/braze preforms.
Polymers are used as adhesives for attaching a die to a substrate. Due to the low CTE of the die and the substrate, a low CTE is desired for the adhesive. A filler of low CTE can be added to the polymer for this purpose. Because of the need to dissipate heat from the die and because polymers are in general thermal insulators, the filler is preferably a thermal conductor. Graphite and AlN are thus suitable fillers.
Solders in the form of solder pastes compete with polymer adhesives for use as screen printable die attach. The attraction of solders lies in their high thermal conductivity. Like polymeric adhesives, solders suffer from a high CTE. Solders suffer in particular because they are fatigued by thermal stresses arising from CTE mismatches. Use of an active (titanium-containing) solder together with a low CTE filler (such as molybdenum particles) alleviates CTE mismatch but it makes the solder less ductile.
Problem Definition
Chip Size, Type of Solder and Fatigue Failure
In industry today two types of solders are used, soft and hard solder. Hard solder consists of Au--Sn, Au--Ge, and Au--Si. Hard solder has a low melting point, with a relatively long fatigue life. However hard solder is expensive and it is only used for chip sizes smaller than 0.25 in. Since the chip is small the differential expansion between the copper and the silicon is small and thus the stress is reduced, with relatively long fatigue life. Due to the cost, even in this case soft solder is used. Soft solder consists of Pb, Sn, In, Ag, Bi, and Cd. They are low cost and also have a low yield stress at low temperature. They plastically deform and have a low fatigue life. Soft solder is normally used for chip sizes between 0.25 in and 1.00 in. If chip sizes are greater than 1.00, then there are two approaches. One is to parallel two chips of half the size, which reduces the thermal expansion stress. However due to close proximity of many joints and power cycling they have electrical failures. The other approach is in the use of low expansion materials such as W, or Mo. How ever the surface still rub against each other due to CTE mismatch, and fatigue failure occurs.
Solder Stress Induced During Assembly
It is well understood that the elements of an electronic package are fabricated forms that are mechanically joined at one temperature and then exposed to different temperature in use. Owing to the differing CTE, the joined materials are subjected to thermal stresses that can fracture component to carrier interface joints causing mechanical and electrical failure. Silicon has a low CTE, compared to the CTE of other packaging materials. During manufacture the temperature is normally raised to 400F. for solder reflow and then cooled to room temperature. This temperature change introduces strain at the solder joints and stress in the components before being used.
Package Distortion Due to Temperature Gradient; (Pure Shear Strain vs Tensile Force)
How rigidly the package is clamped to the heat sink determines the type of strain induced in the solder joints due to the temperature gradient. In FIG. 1, the package is rigidly clamped, and the solder joint is subjected to a shear dominance strain field. In FIG. 2, the package is not rigidly clamped, hence the solder joint is subjected to a perpendicular force in addition to the in plane shear strain. This results in bowing of the electronic component. Note FIGS. 1 & 2 are highly magnified. U.S. Pat. Nos. 4,973,527; 4,262,412; 4,414,418 and 5,098,798 address the formation of fiber bundles.